Codasip, a leader in RISC-V Custom Compute, has announced the release of the Codasip L110, a low-power embedded processor core, alongside the next generation of its processor design automation toolset, Codasip Studio Fusion. The L110 core is engineered to deliver top-tier performance for power-sensitive applications, while allowing for extensive customization to meet specific application needs.
The Codasip L110 core provides significant improvements in performance per watt, boasting up to 50% better efficiency and a 20% reduction in code size compared to similar cores on the market. This makes it particularly well-suited for small-area, low-power applications such as state machine replacements, sensor controllers, and IoT edge devices.
One of the standout features of the L110 is its configurability, offering various trade-off levels between area and performance. It supports standard RISC-V code-size extensions and allows designers to add new instructions without compromising the core’s baseline functionality. This flexibility is facilitated by Codasip Studio Fusion, which introduces a new “Bounded Customization” feature. This feature enables customers to achieve quick time-to-market with high-quality, fully verified RISC-V cores, significantly simplifying the process of integrating custom instructions.
Brett Cline, Chief Commercial Officer at Codasip, emphasized the advantages of customization: “Customization allows designers to introduce new instructions specific to their software workload and significantly improve PPA. Our new core offers best-in-class performance for small-area and low-power applications accompanied by new possibilities for easy and quick customization with no risk to the core functionality. We offer all this in a flexible business model that will not cost you an arm and a leg.”
Codasip Studio Fusion enhances the design and verification process by allowing for segmented configuration options, automated generation of SDKs and HDKs, and improved design automation. This includes new constructs for fusing architectural and microarchitectural descriptions and converting declarative descriptions into low-level logic. These advancements make processor design more accessible and efficient.
