Cadence Design Systems, Inc. (Nasdaq: CDNS) and Taiwan Semiconductor Manufacturing Company (TSMC) have announced a significant expansion of their longstanding collaboration. This collaboration encompasses a wide array of innovative technological advancements aimed at accelerating design processes across various industries, including artificial intelligence (AI), automotive, aerospace, hyperscale, and mobile applications.
Among the key developments unveiled is the enhancement of Cadence’s Integrity 3D-IC platform in collaboration with TSMC. The platform now features a hierarchical 3Dblox specification designed to integrate multiple chiplets into hierarchies for enhanced modularity and design reusability. Additionally, new features have been introduced to streamline chiplet assembly and design, along with an automated alignment markers insertion flow to expedite the design and assembly of stacked chiplets on different interposers and packages.
Certification has also been achieved for Cadence’s digital solutions for TSMC N2 design flow. This suite of solutions includes the Innovus Implementation System, Quantus Extraction Solution, and others, all aimed at optimizing power, performance, and area (PPA) results in AI-driven design workflows. Furthermore, Cadence’s custom/analog design flow has been fully certified for TSMC’s latest N2 Process Design Kit (PDK), underscoring the commitment to providing tools optimized for advanced node designs.
A significant milestone is the release of the Virtuoso Studio N16 to N6 RF migration reference flow, which substantially reduces turnaround time for RF designs. This flow includes purpose-driven instance mapping for rapid retargeting of schematics and the EMX Planar 3D Solver for inductor synthesis and EM extraction. Moreover, Cadence has introduced a comprehensive portfolio of industry-leading IP cores for TSMC’s N3 process, covering die-to-die (D2D) interconnect, memory interfaces, and PCIe 5.0/CXL2.0 and PCIe 6.0/CXL3.0.
The collaboration between Cadence and TSMC has also resulted in significant advancements in EM analysis, with the certification of the EMX 3D Planar Solver for TSMC’s N5 process technology. This certification enables seamless integration into advanced-node IC design flows, facilitating highly accurate EM analysis. Additionally, a new silicon photonics flow has been unveiled to support TSMC’s COUPE technology, enabling the heterogeneous integration of photonics ICs with electrical ICs while minimizing coupling losses.
Chin-Chi Teng, Senior Vice President and General Manager of R&D at Cadence, expressed confidence in the collaboration’s ability to drive innovation, emphasizing the newfound design efficiency and technological advancements. Similarly, Dan Kochpatcharin, Head of the Design Infrastructure Management Division at TSMC, highlighted the collaborative efforts’ role in delivering greater value for advanced SoC designs.
