The chip and silicon IP provider Rambus Inc. (NASDAQ; RMBS) introduces industry’s first HBM4 Memory Controller IP. The new solution extends Rambus’ market leadership in HBM IP with broad ecosystem support. It supports the advanced feature set of HBM4 devices, enabling designers to address the demanding memory bandwidth requirements of next-gen AI accelerators and graphics processing units (GPUs).
“With Large Language Models (LLMs) now exceeding a trillion parameters and continuing to grow, overcoming bottlenecks in memory bandwidth and capacity is mission critical to meeting the real-time performance requirements of AI training and inference,” said Neeraj Paliwal, SVP and general manager of Silicon IP, at Rambus. “As the leading silicon IP provider for AI 2.0, we are bringing the industry’s first HBM4 Controller IP solution to the market to help our customers unlock breakthrough performance in their state-of-the-art processors and accelerators.”
“As heterogenous compute architectures are implemented at an ever-increasing scale to support a wide range of workloads with tremendous amounts of data movement, it is essential that the HBM IP ecosystem continues to extend performance and deliver interoperable solutions to meet the growing needs of customers,” said Arif Khan, senior group director of protocol IP marketing in the Silicon Solutions Group at Cadence. “We are pleased to see Rambus offer an interoperable HBM4 Controller IP solution to support the ecosystem alongside Cadence’s leadership in HBM PHY and solutions performance once the industry transition to this new generation of HBM memory begins.”
“HBM4 will represent a major advancement in memory technology for generative AI and other HPC applications,” said Jongshin Shin, executive vice president and head of Foundry IP Ecosystem at Samsung Electronics. “The availability of HBM4 IP solutions will be critical to paving the path for widespread HBM4 adoption in the market and Samsung looks forward to collaborating closely with Rambus and the wider ecosystem to develop new HBM4 solutions for the AI era.”
“In today’s complex and fast-paced semiconductor design landscape, pre-validated IP solutions are key to achieving first-time silicon success,” said Abhi Kolpekwar, vice president and general manager, Digital Verification Technology division, Siemens Digital Industries Software. “Rambus and Siemens have a long-standing and successful collaboration to help our mutual customers meet their product and business goals, and we look forward to working together to deliver a new generation of best-in-class Rambus HBM4 memory controllers verified with Siemens’ high-quality Verification IP.”
“HBM is a key enabling technology for AI because AI processors and accelerators need high-performance, high-density memory for the massive computational requirements of AI workloads,” said Shane Rau, Research VP for Computing Semiconductors at IDC. “As AI processors and accelerators advance, they will need HBM to advance, too. Seeing HBM4 IP in the market now is a key enabling building block that will be ready for designers working on cutting-edge AI hardware.”
The Rambus HBM4 Controller enables a new generation of HBM memory deployments for cutting-edge AI accelerators, graphics and HPC applications. The HBM4 Controller supports the JEDEC Spec of 6.4 Gigabits per second (Gbps). The Controller is further capable of supporting operation up to 10 Gbps providing a throughput of 2.56 Terabytes per second (TB/s) to each memory device. The Rambus HBM4 Controller IP can be paired with third-party or customer PHY solutions to instantiate a complete HBM4 memory subsystem.
