Rambus Inc. (NASDAQ: RMBS), a chip and silicon IP provision provider, has unveiled its Quantum Safe Engine (QSE) designed to fortify hardware security elements within ASICs, SoCs, and FPGAs. This cutting-edge technology aims to safeguard crucial data center and government hardware against potential threats posed by quantum computers.
The introduction of quantum computing poses a significant risk, potentially compromising current asymmetric encryption methods. To counter this, Rambus’ QSE IP core employs NIST-endorsed quantum-resistant algorithms, offering a robust defense mechanism in the post-quantum computing era.
Neeraj Paliwal, General Manager of Silicon IP at Rambus, emphasized the importance of securing data integrity across various applications in the face of emerging quantum threats. Paliwal stated, “The Rambus Quantum Safe Engine is another important addition to our security IP portfolio helping customers transition to Quantum Safe Cryptography starting today.”
Heather West, PhD, Research Manager of Quantum Computing Research at IDC, highlighted the urgency for organizations to adopt quantum-resistant cryptography, asserting, “Implementing quantum-resistant cryptography now is key for organizations to protect their past, current and future data from quantum computing enabled attacks.”
The Rambus QSE IP offers flexibility, available as a standalone cryptographic core or integrated into the Rambus Quantum Safe Root of Trust IP, providing comprehensive hardware security solutions. It aligns with the National Institute of Standards and Technology (NIST) draft standards for quantum-resistant algorithms (FIPS 203 ML-KEM and FIPS 204 ML-DSA), while also offering SHA-3, SHAKE-128, and SHAKE-256 acceleration. Additionally, for heightened security needs against differential power analysis (DPA) attacks, a DPA version of the QSE IP is available.
