Lattice Semiconductor (NASDAQ: LSCC), the low-power programmable leader, today announced the Lattice MachXO5T-NX family of advanced system control FPGAs designed to address customer challenges related to growing system management design complexity. The latest low-power FPGAs based on the Lattice Nexus platform, MachXO5T-NX FPGAs feature advanced connectivity with PCIe®, increased logic and memory resources, and enhanced security. Combined with class-leading power efficiency, size, and reliability, these new low-power FPGAs bring Lattice’s long-standing leadership in control FPGAs to a broader set of control function designs and applications for enterprise networking, machine vision, and industrial IoT.
“As the pace of technological innovation accelerates and system management designs become more complex, the need for advanced processing capabilities increases,” said Dan Mansur, Vice President, Product Marketing, Lattice Semiconductor. “Lattice MachXO5T-NX FPGAs equip our customers with more capacity, faster I/O, and enhanced security features in the low power, small size envelopes to help them simplify system integration while maintaining power efficiency, compatibility, and performance.”
Key features and performance highlights of the new low power Lattice MachXO5T-NX FPGAs include:
- Control FPGAs with PCIe
- Featuring hardened PCIe Gen 2 interfaces between the host processor and the control FPGA.
- Increased logic and memory resources
- Up to 3.4X more embedded memory (7.2 Mb) than competing FPGAs of a similar class, minimizing the need for external memory.
- Up to 100X more dedicated user flash memory (57 Mb) than competing FPGAs of a similar class to store mission-critical data and parameters.
- Up to 100X lower soft error rate than competing FPGAs of a similar class, improving system reliability for safety-critical applications.
- Robust programmable I/O
- Address challenges of modern CPUs and SoCs lacking the robust 3.3 V I/O signaling support required to communicate with many other devices in system.
- Feature up to 291 general purpose I/O that support early I/O configuration and provide added features such as 1.25 Gbps SGMII, default pull-down, hot socketing, and programmable slew rate for simplified board design.
- Class-leading security
- On-chip multi-boot with bitstream encryption (AES256) and authentication (ECC256).
- Run-time security capabilities not currently available in competitive FPGAs of a similar class.
