Cadence Design Systems, Inc. (Nasdaq: CDNS) has introduced the latest Cadence Palladium Z3 Emulation and Protium X3 FPGA Prototyping systems, heralding a new era of accelerated verification, software development, and digital twin platforms. These systems, successors to the Palladium Z2 and Protium X2, are poised to address the escalating complexity in system and semiconductor designs, offering a significant performance boost to expedite the development timeline for cutting-edge System on Chips (SoCs).
Trusted by leading companies in AI, automotive, hyperscale, networking, and mobile chip sectors, the Palladium and Protium systems have been instrumental in delivering high throughput pre-silicon hardware debug and software validation. The new Palladium Z3 and Protium X3 systems promise over a 2X increase in capacity and a 1.5X performance improvement compared to their predecessors, empowering faster design bring-up and reducing time to market.
Paul Cunningham, Senior Vice President and General Manager of the System Verification Group at Cadence, emphasizes the critical role these systems play in meeting the challenges posed by accelerating technological innovations. He highlights their integration with the Verisium AI-driven Verification Platform, offering the highest verification throughput necessary for expeditious hardware innovations and the development of new technologies like generative AI.
The Palladium Z3 and Protium X3 systems boast enhanced capacity, scaling from 16 million gates to a massive 48 billion gates, enabling comprehensive testing of entire SoCs rather than partial models. Powered by the NVIDIA BlueField DPU and NVIDIA Quantum InfiniBand networking platforms, these systems ensure seamless transition between virtual and physical interfaces, maintaining congruency for efficient testing.
Dhiraj Goswami, Corporate Vice President of Hardware System Verification R&D at Cadence, underscores the systems’ capability to facilitate fast pre-silicon verification and validation of intricate devices. Their innovative silicon and system architecture, combined with modular compile and debug capabilities, enable multiple turns per day, addressing customers’ evolving needs effectively.
Scot Schultz, Senior Director of Networking at NVIDIA, acknowledges the role of NVIDIA networking in accelerating the next-generation Cadence Palladium and Protium systems, pushing the boundaries of capacity and performance for generative AI computing.
The Palladium Z3 system introduces domain-specific apps, including the industry’s first 4-State Emulation App, Real Number Modeling App, and Dynamic Power Analysis App, enhancing system-level accuracy and accelerating low-power verification.
Tran Nguyen, Senior Director of Design Services at Arm, underscores the importance of scalable validation and verification tools in the face of increasing SoC complexity, lauding Cadence’s hardware verification platforms for driving innovation in Arm IP design.
Alex Starr, Corporate Fellow at AMD, highlights the collaboration with Cadence to enhance design productivity and meet time-to-market goals. The incorporation of AMD Versal Premium VP1902 adaptive SoC within the Protium X3 system and AMD EPYC processor-based host servers underscores AMD’s commitment to delivering leadership computing products.
The Palladium Z3 and Protium X3 systems, integral parts of the Cadence Verification Suite, align with the company’s Intelligent System Design strategy, enabling SoC design excellence. Select customers have already deployed these systems, with general availability slated for Q3 2024.
