Cadence Design Systems, Inc. (Nasdaq: CDNS) has announced the expansion of its long-standing collaboration with Taiwan Semiconductor Manufacturing Company (TSMC) to support the development of advanced-node and 3D-IC semiconductor technologies. The partnership aims to accelerate time to silicon through certified design tools and silicon-proven IP for TSMC’s A16, N2P, and N3 process technologies.
As part of the collaboration, Cadence is delivering certified digital, custom/analog, and thermal analysis design solutions for TSMC’s A16 and N2P nodes. These solutions are designed to improve performance and power efficiency in AI chip design, using AI-driven methodologies such as large language model-based design flows. Cadence also offers TSMC9000-certified DDR5 12.8G IP for N2P, reinforcing its position in memory IP.
In the automotive segment, Cadence is providing certified IP for TSMC’s N5A and N3A technologies. These include high-performance interface IPs such as LPDDR5X-9600, PCIe 5.0, CXL 2.0, and multi-protocol SerDes, targeting next-generation automotive applications like ADAS and autonomous driving.
Cadence is also extending its design capabilities to TSMC’s 3DFabric platform with a comprehensive solution for chiplet and system-level design, packaging, and analysis. Certified IP offerings include HBM3E 9.6G and 10.4G solutions on N5/N4P and N3P nodes, as well as Universal Chiplet Express (UCIe) 16G on N3P. Cadence’s Integrity 3D-IC Platform now supports advanced multiphysics analysis, including static timing, power integrity, and thermal optimization, alongside AI-based tools for design planning and chiplet partitioning.
Additionally, Cadence’s Sigrity X and Clarity 3D Solver tools now integrate with the 3D-IC platform to automate compliance and signal integrity analysis, enhancing support for UCIe and HBM interfaces. The EMX® Planar 3D Solver is already certified for N3 and is undergoing certification for N2P.
Beyond silicon design, Cadence continues to invest in “More-than-Moore” innovation. The Virtuoso Studio platform supports analog and RF migration to advanced nodes, while the company also collaborates with TSMC on photonic design using its compact universal photonic engine (COUPE). Cadence is further enabling next-gen design efficiency through GPU-accelerated, cloud-based workflows.
“Our partnership with TSMC reinforces our commitment to accelerating customer success by offering certified design flows and IP across advanced-node technologies,” said Chin-Chi Teng, SVP and GM of Cadence’s Digital & Signoff Group.
Lipen Yuan, Senior Director at TSMC, added, “This collaboration supports our shared goal of helping customers meet complex design challenges and shorten time to market with optimized performance and efficiency.”
