The semiconductor IP for IoT, mobile and automobile SoCs provider, Arasan Chip Systems makes its MIPI Soundwire PHY I/O IP available on an immediate basis. With this IP, Arasan now has the capability of providing Total IP solution for MIPI Soundwire in compliance with the latest Soundwire Specifications v1.2.
A simple, unified audio interface, MIPI SoundWire protocol has evolved to numerous markets, especially mobile applications to replace several high pin-count connections, allowing for scalability and flexibility, improved power consumption, and decreased latency. MIPI SoundWire is ideal for a wide range of devices such as personal computers, high-end cellphones, headphones, and hearing aids, ranging from low-cost, low-bandwidth peripherals to high-performance audio codec.
Arasan’s Soundwire Phy v1.2 comprises PHY Host IP with 1 clock lane, 1 data lane and PHY Device IP with 1 clock lane, 3 data lanes. It seamlessly integrates with Arasan’s Soundwire Host and Device Controller. Arasan’s Soundwire PHY features a programmable delay for high-Z to driving data timing and for the accommodation of time to enable Data output signal edge on Clock input, capability for both synchronous and self-timed turn off data output, one-shot with programmable pulse width for self-timed turn off data output. It supports 1.8V +/-10% supply for IOs and 0.8V +/-10% supply for core.
Arasan’s Soundwire PHY I/O IP is silicon proven and immediately available for FinFET process nodes.
