California-based Arasan Chip Systems, a provider of Total IP solutions for Systems on a Chip (Soc) market announces the immediate availability of their formally verified Sureboot QSPI IP. This Silicon Proven QSPI NOR Flash memory controller IP is an extended version of the SPI protocol.it allows the use of 4 data lanes leading to highly effective overall bandwidth.
Arasan’s QSPI IP provides the user immediate access to flash memory from SPI mode on startup. It can also alternatively be configured for any other mode from SPI to Dual SPI or Quad SPI. An additional DMA command may be issued to copy memory from the flash device to anywhere else on the bus.
Arasan’s QSPI host controller’s unique salient features are:
- Compliant with AMBA AXI3/4 and AXI4-lite protocols. An APB control port interface is available if desired instead of the AXI4-lite control port interface.
- User configurable clock frequency support.
- Designed to support all leading NOR FLASH devices.
- Configurable bus width, Full & Narrow AXI burst support.
- DMA for maximum bus throughput.
- Supports 24 or 32b addressing and User selectable commands.
- Supports Execute in Place flash access protocols.
- Backwards compatible with SPI and Dual SPI devices
