By Ron Black, CEO, Codasip
Shrinking semiconductor process geometries is costing the industry more but they are not delivering the expected and required performance improvements – that’s thanks to the end of Moore’s Law, Dennard Scaling, Amdahl’s limits. For decades, the semiconductor industry has benefited from these ‘laws’ of scaling and corresponding exponential gatecount growth, but in recent years we have seen these laws slowing and their relevance declining.
Gordon Moore also predicted that costs of new process nodes would also scale, but recently with geometries less than 28 nm, costs per million gates have actually risen with the smaller geometries. While we continue to improve transistor density through new techniques, each one adds additional and significant costs to both silicon manufacturing and IC design. While new innovations in materials or circuit design might help, the primary route to improvements can now only come from novel architecture.
At my keynote address at the RISC-V Summit (December 2021) on this topic of Scaling is Failing, I said,
The underlying “semiconductor laws” are failing at a time when advanced manufacturing is becoming prohibitively expensive….The only short-term option is to match hardware to computational workload through heterogeneous computing. RISC-V’s modularity combined with design automation provides a foundation for creating novel processors and domain-specific accelerators. Industry must adapt or die
RISC-V‘s open Instruction Set Architecture (ISA) allows just that specialization through Domain-Specific Accelerators. With RISC-V, designers can tune both the microarchitecture and the ISA, to co-develop hardware and software. By building hardware that suits the needs of the application software, or operating system, it makes it possible to deliver truly optimized performance, power, and area.
Customers today are telling us that they want more heterogeneous compute and domain-specific acceleration. We call this Design for Differentiation.
The use of RISC-V as the basic architecture benefits interoperability with ecosystem partners and ready-made software. On top of that, adding custom instructions enables the developer to tailor a system to suit exactly the situation that they need. That could be a suite of instructions tailored to Neural Networks (AI or ML operations) because that is what the system needs. Or it might be instructions for video processing or audio processing because that is what instructions this system needs.
Chips are designed for a purpose – processors are used for a set of applications. A general-purpose processor will be designed to handle a broad computational workload including an operating system.
Traditional architectures such as x86 and Arm have grown in complexity over decades. However, for many specialized applications much of the general-purpose processor hardware will be wasted consuming unnecessary silicon area and power.
Many applications including AI/ML, video and audio processing, and cryptography require narrowly-defined software workloads. In such cases, a smaller specialized instruction set can be tailored to match the needs of the software. The modular RISC-V ISA with its small base integer set and provision for custom instructions is a great starting point. System developers have seen how adding a small number of custom instructions can deliver huge performance improvements with a low hardware overhead.
The benefit of this specialization is that processor area, instruction memory and power consumption can all be reduced compared with general-purpose cores. This domain specific accelerator approach makes it possible to continue improving processor performance without increasing power and area.
Basic commonality and interoperability avoid fragmentation, and ensures you get the benefits of the RISC-V ecosystem. But for many systems the best processor is one tailored for its task. RISC-V enables that system flexibility.
Apple gave us an excellent example of intelligent co-design for processors. Look at how the company approached the design for its latest Apple MacBook Pro computers: the M1 Pro and M1 Max SoCs were developed in-house to perfectly suit the task and their objectives for the overall system performance – that is, the industry’s highest performance laptops running Mac OS.
From a development point of view, it’s important to be able to convert ideas into real designs as quickly as possible. Designing a processor core from scratch might be daunting, but it is possible to jump start the process by starting with an existing RISC-V core design.
With the right tools and HDL (Hardware Description Language), the designer is able to automate the design of programmable cores. The advantage of using an architectural language is that it can be used to generate both the Software Development Kit (SDK) and Hardware Development Kit (HDK). This allows the tools to rapidly explore ISA and microarchitecture alternatives.
To tailor a core to a particular application, a processor core can be chosen, and the application software profiled with the processor design automation tools. Computational hotspots can be identified, and custom instructions devised to address them. Then the profiling can be repeated, and performance assessed. This process can work iteratively until the custom ISA is stable. The tools can finalize microarchitecture and generate the RTL. Last but not least, a UVM verification environment can be generated to verify the custom processor against a golden reference.
After decades of relying on semiconductor scaling, the industry is at a turning point. Increased performance needs specialized, optimized computational units. As we have seen with customers again and again, customizing RISC-V designs with the right processor design automation enables design teams to achieve their performance, area and power goals efficiently. Industry must adapt to this new reality.
