The developer of highly scalable RISC processor IP for high-end automotive, computing and communications applications, MIPS chooses the embedded development tools and services company, Ashling’s RiscFree Toolchain. The toolchain will support MIPS RISC-V ISA based IP cores. RiscFree, Ashling’s Integrated Development Environment having a complier and debugger for RISC-V based development. The product now has support for MIPS RISC-V ISA based IP cores, enhanced by MIPS’ own proven and tested Core Framework Platform.
“We are delighted to have Ashling RiscFree support for our RISC-V ISA IP cores. Our engineering teams have worked closely together developing the toolchain in parallel with the core IP and believe this can result in rapid time-to-market for our end customers,” said Don Smith, Vice President of Engineering at MIPS.
The Ashling RiscFree toolchain will include support for both code development and debug on MIPS RISC-V IP cores and includes advanced features such as multi-core and multi-cluster support, Linux debug awareness, real-time trace support, and cache awareness. It also comes with a range of Ashling hardware probes supporting debug and trace. In addition, a targeted and optimised GCC toolchain is included and fully integrated into the RiscFree IDE.
“We are excited to see MIPS, one of the first companies to bring a RISC based architecture to the market back in the 1980s, now expanding to offer RISC-V ISA compliant cores. We’ve a long history of working together and believe the support of our market-leading RiscFree Toolchain will help in the rapid market adoption of their MIPS RISC-V ISA cores,” said Hugh O’Keeffe, CEO of Ashling.
