The Finnish SoC Hub consortium develops the first System on Chip (SoC). The partners will now focus on improving the design, automation and performance of the SoC. The first of the three chips to be developed will be ready for the market in early 2022. This project will strengthen the European technology sovereignty.
The SoC Hub initiative was launched last year. It is coordinated by Tampere University, Finland, and Nokia and comprises CoreHW, VLSI Solution, Siru Innovations, TTTEch Flexibilis, Procemex, Wapice and Cargotec as partners. The consortium is set to develop the domain of SoC design as a leader in Europe and to improve its competitive position in Finland.
SoC Hub project aims at the rapid prototyping for new ideas, for example, in the Internet of Things (IoT), machine learning and 5G and 6G technologies in silicon.
“The SoC has been developed using the same methods that are used in industrial production, such as design for testability, extensive verification and focusing on system-level integration instead of single modules,” says Ari Kulmala, professor of practice in SoC design at Tampere University. He also added that the chip includes a development kit, and it can be integrated into a wide range of other systems. It can be tested by external stakeholders
The newly launched Ballast chip is the first in a series of three chips that will be manufactured by TSMC using its recent 22nm Ultra Low Leakage process. It is especially suited for IoT and Edge devices. Ballast contains different RISE-V CPU cores, a Digital Signal Processor, an AI accelerator, rich sensor-like interfaces and an extension interface to FPGA. A full software stack – including drivers, software development tools and chip debugging support – has also been implemented. The chip supports both real-time operating systems and Linux simultaneously.
“It has been a pleasure to work with the SoC Hub team. They have been extremely quick to develop the chip, and the quality of the work has been top class,” says Bas Dorren, Director of Business Development at imec.IC-link, part of imec (an R&D hub for nano and digital technologies).
Another two chips are taped out in the next two years.
The chip was created in a very short time despite its large size.
“A great deal of work has been done to enable seamless collaboration between the University and company partners. Several early career researchers have participated in designing Ballast and have therefore had the opportunity to apply the knowledge they acquired from their studies in an industrial project,” says Timo Hämäläinen, head of the Computing Sciences Unit at Tampere University.
Funded by Business Finland, the three SoCs are slated to be taped out by the end of 2023. Use cases for the chips will be planned together with the project consortium.
“In the next phases of the project, we will be able to focus even more on the systematics, automation and performance of the SoCs. Despite having achieved our first goal, we continue moving forward right away. The time to invest in SoC development is now, not tomorrow,” emphasises Timo Hämäläinen.
