Rapidus Corporation establishes a clean room within Seiko Epson Corporation’s facility in Chitose, Hokkaido. This research, development, design, manufacture and sales of advanced logic semiconductors firm will also open a R&D center for semiconductor post-processing called Rapidus Chiplet Solutions (RCS).
Adjacent to the Rapidus Innovation Integration for Manufacturing (IIM) foundry, Seiko Epson Chitose Plant at Bibi, Chitose City was unveiled at a groundbreaking ceremony. The clean room spreads at an area of nearly 9,000m2 (96,875 square feet). This new facility will enable Rapidus to develop mass production technologies for chiplet packages.
Rapidus will begin installing manufacturing equipment in April 2025, with R&D activities scheduled to begin in April 2026. RCS will have pilot lines for the FCBGA, Si interposer, RDL, and hybrid bonding processes, and will conduct additional R&D on mass production technologies, including equipment automation.
In terms of the development of back-end processes and chiplet integration technologies, the Ministry of Economy, Trade and Industry and New Energy and Industrial Technology Development Organization approved the project for the “Development of Chiplet Package Design and Manufacturing Technology for 2nm Generation Semiconductors” in April 2024, and development of core technologies such as chiplet integration and 2.5D/3D packaging is progressing.
In June 2024, Rapidus signed a partnership with IBM not only for front-end processes but for chiplet technology. In addition, Rapidus is collaborating with organizations across four countries, including LSTC, AIST, the University of Tokyo, Fraunhofer in Germany and A*STAR IME in Singapore to further packaging advancements.
