YorChip, Inc. has revealed its inaugural Edge AI Compute Chiplet, featuring intellectual property (IP) sourced from Semidynamics, a leading provider of RISC-V IP based in Barcelona. The chiplet incorporates Semidynamics’ High-Performance High-Bandwidth Quad Core IP with 4 Atrevido 423 cores, V8 SMD VPUs, and T16 SMD Tensor Units, offering a noteworthy 10 Int8-TOPS per chiplet.
Engineered to meet the demands of high-performance edge AI applications, the target technology for the YorChip Edge AI Compute Chiplet is 12nm, with a sub 25mm2 die size. The chiplet is designed to provide scalable performance and cost-effectiveness, addressing the key requirements of the dynamic Edge AI landscape.
The Chiplet market is anticipated to witness substantial growth, projected to exceed US$47 Billion by 2031, according to Transparency Market Research. This forecast underscores the increasing adoption of chiplet technology, driven by its potential for cost reduction and improved yields compared to traditional system-on-chip (SoC) designs.
Kash Johal, CEO, and founder of YorChips, explained the strategic collaboration with Semidynamics, citing their focus on customizable 64-bit RISC-V processor IP and expertise in supporting AI/ML workloads. Johal highlighted the versatility of the YorChip Edge AI Compute Chiplet, stating, “Coupled with our UCIe PHY and low latency switching fabric, customers can cluster up to 16 Compute Chiplets to support 100 Int-8 TOPS.”
Semidynamics’ CEO, Roger Espasa, emphasized the targeted applications of their RISC-V Quad Core IP in automotive, robotic, drone, and high-performance edge AI markets. The collaboration with YorChip provides an avenue to showcase their latest IP in a Chiplet application, enabling customers to explore and utilize their technology.
Brian Faith, CEO of QuickLogic, acknowledged the growing demand for design flexibility, higher performance, and bandwidth in the semiconductor industry. Faith noted the appeal of the YorChip Edge AI Compute Chiplet to FPGA Chiplet customers, particularly due to the built-in UCIe interfaces.
