In a groundbreaking move, TSMC, a leading semiconductor manufacturer, unveiled pioneering advancements in 3D Integrated Circuit (IC) technology during its 2023 Open Innovation Platform (OIP) Ecosystem Forum. At the heart of these developments lies 3Dblox 2.0, an open standard designed to streamline 3D IC design solutions. Introduced last year, this innovative standard has evolved significantly, enabling designers to conduct early power and thermal feasibility studies for entire 3D systems — a milestone achievement within the industry.
TSMC’s commitment to fostering industry-wide collaboration is evident through the establishment of the 3Dblox Committee, an independent standard group. Collaborating with key partners such as Ansys, Cadence, Siemens, and Synopsys, this committee aims to create specifications that allow system design with chiplets from diverse vendors. These specifications are accessible to designers via the 3dblox.org website, promoting interoperability of Electronic Design Automation (EDA) tools.
Additionally, TSMC highlighted the remarkable progress made by its 3DFabric Alliance, an initiative aimed at advancing semiconductor design, memory modules, substrate technology, testing, manufacturing, and packaging. Notable achievements include collaborations with major memory partners such as Micron, Samsung Memory, and SK hynix. These collaborations have led to enhancements in High Bandwidth Memory (HBM) technologies (HBM3 and HBM3e), catering to the growing demands of generative Artificial Intelligence (AI) systems by providing increased memory capacity.
Furthermore, TSMC’s collaborations with substrate partners IBIDEN and UMTC have resulted in the development of a Substrate Design Tech file, simplifying automatic substrate routing for enhanced efficiency and productivity. These efforts are part of a broader collaboration with substrate and EDA partners, aiming to achieve a tenfold increase in productivity through automatic substrate routing and Design for Manufacturing (DFM) enhancements to reduce stress hotspots in substrate design.
TSMC has also engaged in strategic partnerships with automatic test equipment providers Advantest and Teradyne to address diverse challenges in 3D testing. These collaborations aim to reduce yield loss and enhance power delivery efficiency for chiplet testing. Synopsys and other partners are working with TSMC on a silicon demonstrator, with the goal of achieving a tenfold increase in testing productivity through high-speed test access for 3D stack testing via functional interfaces.
TSMC’s strides in 3D IC technology reflect its dedication to collaborative innovation, marking a significant leap forward in the evolution of semiconductor technology. The developments showcased at the OIP Ecosystem Forum have far-reaching implications for the future of artificial intelligence, high-performance computing, and mobile applications.
